This invention relates to circuitry and methods for receiving a high-speed data signal. For example, the circuitry of this invention may be provided on a programmable logic device (“PLD”), and the methods of the invention may be methods of operating the circuitry.
A so-called high speed serial interface (“HSSI”) may be used to communicate between devices in a system. Typically, it is the intention for the transmitter in such a system to transmit a digital (binary) signal having two distinctive levels, and well-defined (i.e., very steep) transitions from either of these levels to the other level. Such steep transitions are essential to transmitting data at high speed. The medium that conveys the signal from the transmitter to the receiver usually imposes losses on the signal being transmitted. These losses generally include diminished signal amplitude and reduced transition steepness. To maintain accurate, high-speed data transmission, it is necessary for the circuitry to compensate for these losses.
One way to do this is for the transmitter to give the signal pre-emphasis. This means giving the signal extra energy immediately after each transition. The extra energy can be extra amplitude (voltage) and/or current. At very high data rates (e.g., in the range of about 3 gigabits per second (3 Gbps) and above), pre-emphasis can have the disadvantage of giving the signal being transmitted high frequency components that can undesirably couple to other circuitry.
To avoid the above-described disadvantages of pre-emphasis, it may be preferable to use what is called equalization at the receiver. Equalization circuitry is typically among the first circuitry that the incoming signal sees when it reaches the receiver. Equalization circuitry is designed to respond strongly and rapidly to any transition detected in the received signal. This strong and rapid response restores the original steepness to these transitions, thereby making it possible for further circuitry of the receiver to correctly interpret the signal, even at the very high data rate of that signal.
Especially in the case of equalization circuitry that is intended for inclusion in a PLD, a need exists for such circuitry that can perform over a wide range of data rates, and that can compensate for signal losses of various kinds and degrees. This is so because PLDs are typically designed for a wide range of possible uses. The exact parameters of any particular use are not known in advance. The PLD must be customizable by the user and/or be self-adapting to meet the requirements of each particular use within the relatively wide range of possible uses. Improved equalization circuitry is therefore sought for this type of application.